In most manufacturing processes for integrated circuit memory devices, the memory devices are subjected to a quality testing process after fabrication. In some manufacturing processes, this quality testing process includes subjecting the memory devices to a burn-in test and to an op-life test. In general, the burn-in test is designed to accelerate the failure of those memory devices that would have failed early within the device lifetime, sometimes referred to as infant-mortality. By accelerating the stress on the memory devices, the burn-in test identifies these faulty devices in a reduced time-frame. In general, the op-life test follows burn-in and is designed to accelerate the failure of memory devices at the end of the device lifetime, sometimes referred to as wear-out. Thus, the op-life test provides information about the average lifetime of the memory devices to insure the memory devices will work properly for the desired period of time.
It is desirable to stress the memory devices during burn-in such that substantially all of the memory devices that are going to fail prior to the desired device lifetime will fail during the burn-in test. However, it is undesirable to place too much stress on the memory devices during burn-in test because the yield can be reduced unnecessarily. It is also undesirable to place too little stress on the memory devices during burn-in because memory devices will fail during the op-life test and present a quality problem.
One point of failure for memory devices can be a yield loss due to failure of large on-chip capacitors such as due to current leakage from pinholes in the capacitor oxide. Memory devices often have such large storage/filter capacitors to serve to supply current and stability for a high voltage supplies. This use for voltage supplies requires such storage/filter capacitors to be as large as possible in order to produce stability in the supplied voltage level. For example, one such storage/filter capacitor can be used for an internal boosted voltage level, VPP, to drive word line and sense amplifier selection. In some memory device designs, the high voltage plate of this storage/filter capacitor is connected to a node supplying the high voltage level, VPP, and the low voltage plate is connected to ground potential, VSS. Because of the large voltage difference between VPP and VSS, the storage/filter capacitor can see stress during burn-in test that exceeds the stress seen by other structures in the memory device. This higher stress is problematic in that it can produce unnecessary failure of memory devices during burn-in test.
It is desirable to reduce unnecessary failure of memory devices caused by large on-chip capacitors being over-stressed during burn-in test of the memory devices. In particular, it is desirable to reduce unnecessary failure caused by stress on high voltage storage/filter capacitors in the memory device. Conventional solutions to this problem include connecting the low voltage plate of the high voltage storage/filter capacitor to a positive external power supply. This reduces the voltage across the storage/filter capacitor which lowers the stress on the capacitor. However, this solution causes stability problems due to slew in the external voltage power supply and causes quality problems due to understressing of the storage/filter capacitor during burn-in test.